1. Field of the Invention
The present invention relates to a data storage circuit, and more particularly to potential setting of bit lines or match lines.
2. Description of the Background Art
In a static random access memory (SRAM) of the background art, when data is written into the SRAM or read out from the SRAM, bit lines are first precharged.
Usually, precharge of the bit lines is performed during a period while a clock signal indicates “0” level and write or read of data is performed during a period while the clock signal indicates “1” level (see Japanese Patent Application Laid-Open No. 2001-344979, Paragraph No. 0063, FIG. 1 and the like).
Recently, however, with thinning of gate oxide films in size reduction of devices, in the background-art technique where the precharge of the bit lines is performed in a standby state of the SRAM (during the period while no access is made to the SRAM), a gate leak current flowing in a gate oxide film or the like (understood as a standby current) in the standby state tends to increase and a standby power consumption of the SRAM disadvantageously increases as the standby current increases.